Electronic Design

Tool Generates RTL Code From Untimed C++

The complexity of compute-intensive applications is driving the move to system design at the algorithmic level. With the release of the Catapult C synthesis tool, Mentor Graphics now offers the core ...
EDN

Physical RTL optimization solves problems early

While most of the ASIC industry is focused on solving timing and congestion problems at the netlist level, LSI Logic has developed and deployed an innovative methodology to resolve these physical ...
Electronic Design

Predictive-Analysis Tool Sniffs Out Gate-Level Problems In RTL Code

Thanks to a fast, built-in synthesis engine, Atrenta's SpyGlass 3.0 predictive-analysis tool detects very complex structural problems in register transfer level (RTL) code that would otherwise only ...
Semiconductor Engineering

Shift Verification Left: AI Tools For Faster, Smarter Chip Design

If designers can verify individual blocks before subsystem integration, the verification team can focus on complex ...
Design-Reuse

Tensilica Announces Major IC Design Automation Breakthrough, The Automatic Generation of Optimized Programmable RTL Engines from Standard C Code

SANTA CLARA, Calif. - Sept. 6, 2004 - Tensilica(R), Inc. today announced that it has achieved a major design automation breakthrough - the automated design of optimized configurable processors from ...
Design-Reuse

Real-World Reuse: RTL Recycling

In the real world of electronic product design, time-to-market can have a large impact on success. To facilitate production speed, RTL from existing projects is often recycled for use in the new ...
Semiconductor Engineering

Do You Know For Sure Your RISC-V RTL Doesn’t Contain Any Surprises?

Given the relative novelty and complexity of RISC-V RTL designs, whether you are buying a commercially supported core or downloading a popular open-source offering, there is the small but non-zero ...