Morning Overview on MSN

Samsung readies PCIe 5.0 QLC SSD with a RISC-V based controller

Samsung is preparing a PCIe 5.0 SSD that pairs quad-level cell (QLC) flash memory with a RISC-V-based controller, a combination that could reshape cost and performance expectations for storage in ...
Design-Reuse

CHIPS Alliance to Collaborate with RISC-V to Standardize an Open Unified Memory Leveraging OmniXtend

SAN FRANCISCO, Dec. 8, 2020 – CHIPS Alliance, the leading consortium advancing common and open hardware for interfaces, processors and systems, today announced that the organization will highlight ...
Hosted on MSN

British startup launches low-power RISC-V processor design to address the twin problems of memory and energy; promises up to 50% faster calculation speeds

Blueshift’s BlueFive RISC-V processor addresses Memory and Energy Walls BlueFive claims faster calculations, lower energy use via data optimization Validated design integrates memory controller, CPU ...
Semiconductor Engineering

Tag-Based Memory Verification System for RISC-V (Inha Univ., Intel Labs et al.)

A new technical paper titled “Efficient Hardware-Assisted Heap Memory Safety for Embedded RISC-V Systems” was published by researchers at Inha University, Intel Labs, Electronics and ...
Semiconductor Engineering

Rowhammer Bit Flips On A High-End RISC-V CPU (ETH Zurich)

“The first high-end RISC-V CPU with DDR4 support has been released just a few months ago. There are currently no Rowhammer studies on RISC-V devices and it is unclear whether it is possible to ...