Semiconductor Engineering

Gem5 Simulation Environment With Customized RISC-V Instructions for LIM Architectures

A new technical paper titled “Simulation Environment with Customized RISC-V Instructions for Logic-in-Memory Architectures” was published by researchers at National Tsing-Hua University, Politecnico ...
Electronics Weekly

SiFive approves Imperas Risc-V simulation models

Risc-V intellectual property creator SiFive has qualified models for its core portfolio from Oxford-based Imperas Software – as well as signing a distribution deal with Valtrix. Imperas’ models for ...
Business Wire

Aldec and Codasip at Embedded World: Showcasing an Integrated UVM Simulation Environment for Verifying Custom Instructions with RISC-V Cores

NUREMBERG, Germany--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, is exhibiting at Embedded World in Nuremberg, ...
Semiconductor Engineering

Linting RISC-V Designs

As the open-source RISC-V instruction set architecture (ISA) continues to gain momentum, the growing number of RISC-V design solutions and their flexibility creates a problem when choosing the most ...
Geeky Gadgets

MIPS RISC-V P8700 and I8500 development kits are now available

With the rise of RISC-V architecture, developers are seeking efficient and flexible solutions for their processor needs. MIPS RISC-V IP Core Technology is at the forefront of this revolution, offering ...
Business Wire

Cobham Gaisler Successfully Verifies Its First RISC-V Processor, NOEL-V, Using Aldec’s Riviera-PRO for HDL Simulation

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, today announced that Cobham Gaisler has ...
Embedded

3 trends for 2024: AI drives more edge intelligence, RISC-V, & chiplets

With CES 2024 set to open its doors in Las Vegas just a week from now, it’s clear that this year is all about evolving consumer electronics products that rely on ever more connected, embedded edge ...
The Next Platform

Strong Showing for First Experimental RISC-V Supercomputer

A European team of university students has cobbled together the first RISC-V supercomputer capable of showing balanced power consumption and performance. More importantly, it demonstrates a potential ...
EDN

RISC-V’s CPU Verification Challenge

RISC-V is gaining attention throughout the semiconductor industry. It offers the lure of an open-source solution that anyone can leverage to create their own CPU or custom accelerator. Of course, dig ...