Using different processors in a system makes sense for power and performance, but it’s making cache coherency much more difficult. Cache coherency is becoming more pervasive—and more problematic—as ...

Part 1: A look at the impact of communication across multiple processors on an SoC and how to to make that more efficient. Managing how the processors in an SoC talk to one another is no small feat, ...

With silicon clock scaling largely dead thanks to the laws of physics, computer scientists and chip designers have had to search for performance improvements in other areas -- typically by improving ...

A fundamentally new approach to cache coherence has been released -- the first in more than three decades. Whereas with existing techniques, the directory's memory allotment increases in direct ...

In the first part of this series on the proposed Cache Coherence Interconnect for Accelerators (CCIX) standard, we talked about the issues of cache coherence and the need to share memory across ...

Scaling processing performance beyond the frequency and power envelope of single core systems has led to the emergence of multi-core clusters. Data access management within such processing systems ...

Moreover, cache coherence is an especially important protocol to verify. A cache-coherence bug could result in a silent data corruption that would disrupt system functionality. A formal tool for ...

The past decade or so has seen some really phenomenal capacity growth and similarly remarkable software technology in support of distributed-memory systems. When work can be spread out across a lot of ...

If multiple devices, such as the CPU and peripherals, access the same cacheable memory region, cache and memory can become incoherent. This is illustrated in Figure 7. Suppose the CPU accesses a ...

In a modern, multicore chip, every core -- or processor -- has its own small memory cache, where it stores frequently used data. But the chip also has a larger, shared cache, which all the cores can ...